This chip startup recently raised $135M in an incalculable AI bet — it’s memory

Every time you ask ChatGPT a question, your request triggers a data transfer race. Information leaves memory, goes through the CPU for pre-processing, goes to the GPU for hard calculations, and then back – and that entire journey repeats every single word the AI ​​produces.

The bottleneck is systematic – it means navigating some of the most expensive and power-intensive chips in the industry for every single application. That inefficiency is exactly what XCENA, a startup with offices in South Korea and the US, is trying to solve. The four-year-old startup has designed a chip that puts computing capabilities closer to DRAM — fast, short-term memory chips that store data the processor is actively using — allowing common data tasks to be handled near memory, without expensive round-trips between CPUs, GPUs, and memory.

If it works at scale, the cost implications of AI infrastructure can be huge, which largely explains the enthusiasm of investors across the country. Indeed, XCENA recently raised $135 million in Series B at a value of $570 million, bringing its total to $185 million.

XCENA CEO Jin Kim founded the startup in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, all veterans of Samsung and SK Hynix, the memory giants that supply the chips that power Nvidia’s GPUs. “CPUs and GPUs have both been smart for decades. Memory has never been. XCENA wants to change that,” said Kim in an interview with TechCrunch. “Recent increases in memory prices and related shares point to a broader shift in AI infrastructure to memory-centric architecture,” he added. (This month, the three companies that dominate the global memory chip market — Samsung, SK Hynix, and Micron — each surpassed the trillion-dollar mark for the first time.)

XCENA is betting its business on the idea that “thinking is not just a computing problem; it’s increasingly a memory-enhancing problem,” Kim said.

The XCENA chip, MX1, connects to the CPU via CXL (Compute Express Link) – in fact a dedicated clear path between the processor and memory – to process data before it needs to leave the memory module. It brings the computer to the data, not the other way around. The company says that what used to require 10 servers can run on one.

“While GPUs are successful in matrix multiplication – difficult calculations after AI model training – a large part of the orchestration of the surrounding data, including pre-processing, KV cache management. [the system that stores prior conversation context so a model doesn’t have to reprocess it]and data storage, still running on CPUs. Our chip handles those functions directly within the memory module itself,” Kim said.

The demand for memory solutions has grown since the second half of last year, and the company believes that time is working for it.

Talks with several global memory vendors are in the early stages, although Kim declined to name them. The company’s ideal hyperscaler customers spend tens of billions a year on AI infrastructure, where even a small gain in memory efficiency can mean hundreds of millions in savings.

The MX1 is still a prototype. Mass production chips are scheduled to roll off Samsung’s production lines in late 2026, with the company expecting to generate revenue starting in 2027.

While neural processing unit (NPU) makers are competing to challenge Nvidia with the training load, XCENA is targeting the memory layer that sits underneath it all.

XCENA’s closest competitors include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory interconnects. Marvell is a big, established player already operating in the same space, Kim said, adding that the difference comes down to intellectual property. “We have thousands of cores,” Kim said. Based on the public specification, Marvell’s approach relies on several cores of general purpose in comparison.

Those cores are built on RISC-V – an open source chip blueprint – and specially optimized for data processing., each context is kept small and functional. Besides the cores themselves, XCENA designs its own internal memory, interconnect bus, and DRAM controller – a level of direct integration that many chip companies, including major competitors, often outsource.

Seoul-based VC firms Altinum and IMM Investment co-led the Series B round, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company, which has more than 90 employees across Pangyo offices, a technology center outside Seoul, and Sunnyvale, is also in talks with international investors about additional funding.